module tyrc_alu #(
    `include "tyrc_param.v")(
    input [WORD_WD -1:0]in0,
    input [WORD_WD -1:0]in1,
    input [4       -1:0]op,
    output[WORD_WD -1:0]out,
    output              zero_flag
);

assign out = (op == ADD) ? in1 + in0:
             (op == SUB) ? in1 - in0:
             (op == AND) ? in1 & in0:
             (op == NOT) ? ~in0: 
                           in0;

assign zero_flag = (out == {WORD_WD{1'b0}});

endmodule
